//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov  6 21:40:23 MST 2019
//Date        : Tue Nov 26 15:03:21 2024
//Host        : Laptop-LZY running 64-bit major release  (build 9200)
//Command     : generate_target dds_wrapper.bd
//Design      : dds_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module dds_wrapper
   (CLK,
    Q
    );
  input CLK;
  output [7:0]Q;

  wire CLK;
  wire [7:0]Q;
  
  dds dds_i
       (.CLK(CLK),
        .Q(Q));
endmodule
